
Deepak Arora
About
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A solution-driven technologist with expertise in structure-process-property relationships, rheology and capability development for polymers/composites with experience in electronic packaging. 
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Adept at material, design and process development for wafer as well as panel level packaging, including fan-in, fan-out, flip-chip (coreless and thin core) and die-embedding technologies. 
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Experienced in working with domestic and overseas cross-functional teams and partners. 
Work Experience
February 2020 - Current
August 2016 - May 2018
October 2011 - May 2016
Associate Professor
INDIAN INSTITUTE OF TECHNOLOGY JODHPUR, Jodhpur, Rajasthan, India
Department of Chemical Engineering
Research Areas: Polymer nanocomposites for electronic packaging and healthcare
Research Packaging Engineer
FUJIFILM ELECTRONIC MATERIALS, North Kingstown, RI, USA
Developed materials for advanced electronic packaging. Successfully formulated a polymer dielectric platform that passed reliability at an industrial consortium led by a partner lab.
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Process Development Lead 
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Company: Intel Corporation, Chandler, AZ, USA 
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Role: Substrate Technology Development 
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Enabled high-volume manufacturing, saving $4 billion and enhancing competitive advantage. 
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Developed coreless and die-embedding technologies, achieving 90% yield in technology development. 
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Received nine departmental, two divisional, one group, and seven peer-to-peer awards. 
Education
MS - PhD
August 2004- May 2010
Polymer Science and Engineering, University of Massachusetts Amherst 
Thesis: Structure-property evolution during polymer crystallization (advisor: H. Henning
Winter)
BTech - MTech
July 1999 - June 2004
Chemical Engineering, Indian Institute of Technology Madras
Honors and Awards
Invited Talks and Workshops
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Polymer Dielectrics for Semiconductors: Opportunities and Challenges in Advanced Electronic Packaging 
 Invited talk, Department of Chemical Engineering, IIT Ropar, 2024.
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Thermal Analysis and Rheology – Hot Stage Microscopy 
 Invited virtual short course, NATAS, Thermal Analysis Forum of Delaware Valley (TAFDV), 2022.
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Innovation in IC Packaging – India’s Perspective & Approach 
 Invited panelist, Workshop at Semiconductor Lab (SCL), Mohali, 2022.
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Advances in Electronic Packaging with C4DFED 
 Invited talk, IIT Mandi, 2022.
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Advances in Electronic Packaging 
 Invited talk, Semiconductor Laboratory (SCL), Mohali, 2022.
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Thermal Analysis Forum of Delaware Valley 
 Invited virtual poster evaluation session, 2022.
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International Colloquium on Technology Readiness for High Volume Chip Manufacturing 
 Invited virtual talk, ICTFab, organized by IIT Mandi, 2021.
Recognitions and Awards
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Department Recognition, Intel Corporation - 
Enabling a process to improve inline patterning yield by 10%, 2015. 
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Enabling a process to reduce dielectric cracks to prevent reliability failures, 2015. 
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Developing a factory capability for 2D ID laser mark on substrates to facilitate unit-level tracking for internal yield segmentation and assembly process performance correlation, 2014. 
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Enabling externally procured notched CCL cores as a substitute for internal notching, leading to significant cost savings, 2014. 
 
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Technology Manufacturing Group Excellence Award, Intel Corporation 
 Contributions to substrate technology and core-less technology development, 2014.
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Assembly & Test Technology Development Divisional Recognition, Intel Corporation 
 Developing and implementing a combined change process to improve dielectric adhesion with electro-less deposited copper, 2013.
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Finalist for the AkzoNobel Student Award 
 Polymeric Materials: Science and Engineering Program, American Chemical Society, 2010.
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GATE Achievement 
 Secured a place among the top 2.5% of aspirants in the National Graduate Test in Engineering (GATE), 2002.
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Entrance Examination Achievement 
 Ranked among the top 1% of aspirants in the entrance examination for Indian Institutes of Technology, 1999.
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State Merit List Award 
 Awarded a silver medal for attaining sixth place in the State's merit list out of 200,000 entrants, 1996.
